1. Field of the Invention
The invention relates to a mode-selecting apparatus for selecting a first mode or a second mode in a display unit, a display apparatus including the mode-selecting apparatus, and a method of selecting a first mode or a second mode in a display unit.
2. Description of the Related Art
For instance, Japanese Patent Application Publication No. 10-148812 (A) has suggested a liquid crystal display device having a function of automatically judging whether images are displayed in a liquid crystal display panel in accordance with either a vertical synchronization control (VSC) signal and a horizontal synchronization control (HSC) signal or a data-enable (DE) signal.
In the suggested liquid crystal display device, if VSC and HSC signals are input into a liquid crystal display panel, the detection of synchronization is carried out in accordance with the VSC and HSC signals, even when a DE signal is input into a liquid crystal display panel.
The suggested liquid crystal display device is designed to count a number of dot clocks received in a high level period or a low level period of the VSC signal in order to judge whether the VSC signal, the HSC signal or the DE signal is input thereinto. If a number of dot clocks is greater than a predetermined number, the liquid crystal display device judges that the VSC signal is not received. If a high period and a low period of the HSC and DE signals are longer than a predetermined period, the liquid crystal display device judges that the HSC and DE signals are not received.
Since the above-mentioned liquid crystal display device is designed to carry out the detection of synchronization in accordance with the VSC and HSC signals, even if the DE signal is input into the liquid crystal display device, the liquid crystal display device is accompanied with a problem that it fails to accomplish the detection of synchronization, if the DE signal is input thereinto, and further if one of the VSC and HSC signals is input thereinto.
That is, when the liquid crystal display device receives only the VSC and DE signals (namely, when the HSC signal is not input), or when the liquid crystal display device receives only the HSC and DE signals (namely, when the VSC signal is not input), the liquid crystal display device cannot accurately judge a synchronization signal as a reference signal.
Furthermore, since it is necessary in the above-mentioned liquid crystal display device to count a number of dot clocks associated with one frame in order to judge whether the VSC signal is input thereinto, a circuit size of a counter for counting a number of dot clocks is unavoidably increased.
Japanese Patent Application Publication No. 2001-83927 (A) has suggested a display unit including a first circuit for decoding image signals to thereby output a digital image signal, a synchronization signal, a panel enable signal and a dot clock signal, a second circuit for identifying a polarity of the panel enable signal and outputting a signal having a fixed polarity, the first counter for measuring a difference in phase between leading and trailing edges of the panel enable signal in the unit of a dot clock to thereby detect a horizontal resolution, and a second counter for measuring a period of time during which the panel enable signal is maintained to thereby detect a vertical resolution.
Japanese Patent Application Publication No. 2001-92401 (A) has suggested a mode-selecting circuit comprised of a horizontal dot counter having a first divider, and a vertical line counter having a second divider. Until the horizontal dot counter and the vertical line counter overflow, the first and second dividers are not driven, and counts counted by the horizontal dot counter and the vertical line counter are input into an input-mode identifier. If the horizontal dot counter overflows, the first divider is driven, and the count counted by the horizontal dot counter is compensated for with a dividing ratio of the first divider. The thus compensated count is input into the input-mode identifier. If the vertical line counter overflows, the second divider is driven, and the count counted by the vertical line counter is compensated for with a dividing ratio of the second divider. The thus compensated count is input into the input-mode identifier.
Japanese Patent Application Publication No. 2001-236052 (A) has suggested a display driver for producing a control signal to apply predetermined signal-processing to an image signal in accordance with a synchronization signal included in the image signal, including a first unit which produces a first signal indicative of variance in a timing of a first synchronization signal included in the image signal, a second unit which produces a first reference signal in accordance with the first synchronization signal, a third unit which determines a tolerance for timing variance of the first synchronization signal, in accordance with a second synchronization signal independent of the first synchronization signal, a fourth unit which produces a second reference signal in accordance with the second synchronization signal, a fifth unit which judges whether a predetermined timing of the first signal is in the tolerance, and a sixth unit which selects one of the first and second reference signals in accordance with the result of the judge carried out by the fifth unit, and outputs the selection as the control signal.
Japanese Patent Application Publication No. 2002-278493 (A) has suggested an image display device including a line-counting circuit which counts data enable signals indicating that image signals are valid, and judges whether a number of the thus counted data enable signals is equal to or greater than a predetermined number, a controller which, when a number of the thus counted data enable signals is equal to or greater than the predetermined number, detects vertical synchronization by virtue of the data enable signals to output a vertical synchronization signal, and a scanning circuit which vertically scans an image-display area in accordance with the vertical synchronization signal.
Japanese Patent Application Publication No. 7-134571 (A) has suggested a driver circuit for driving a liquid crystal panel in each of fields with an image signal, including first means for counting horizontal synchronization signals, based on vertical synchronization signals of image signals to be input in order to obtain a number N of drive horizontal lines in a field, second means for detecting that a total number M of drive lines of the liquid crystal panel is greater than the number N, and third means for masking reset signals for resetting the first means, from inputting thereinto, while the number M is greater than the number N.
Japanese Patent Application Publication No. 10-83174 (A) has suggested a display unit which identifies a display mode of an image signal in accordance with a synchronization signal, including a first device for separating synchronization signals from an input image signal, a second device for generating a clock signal, a third device for controlling the synchronization signals, a fourth device for measuring a cycle of a horizontal synchronization signal, a fifth device for measuring a cycle of a vertical synchronization signal, a memory for storing the measured cycles, and a sixth device for identifying a display mode in accordance with the cycles of the synchronization signals.
Japanese Patent Application Publication No. 10-260667 (A) has suggested a display device in which if a data enable signal is not received in a vertically scanning period, switching frame memories in accordance with a next vertical synchronization signal is not carried out.
Japanese Patent Application Publication No. 11-69263 (A) has suggested a vertical blanking producing circuit including a first counter which counts dot clocks synchronizing with a horizontal synchronization signal, and is reset with a vertical synchronization signal, a first decoder which decodes signals transmitted from the first counter, and outputs a pulse, a second counter which counts horizontal synchronization signals, and is reset with a vertical synchronization signal, a second decoder which decodes signals transmitted from the second counter, and outputs a pulse, and a first S-R-FF circuit which is set by the pulse transmitted from the first decoder and reset by the pulse transmitted from the second decoder, and outputs a vertical blanking signal.
Japanese Patent Application Publication No. 11-143448 (A) has suggested a memory controller including first and second counters each having reset and enable functions, and a block which detects vertical and horizontal synchronization signals. The first counter is reset by the vertical synchronization signal detected by the block. An enable signal of the first counter and a reset signal of the second counter are controlled by the horizontal synchronization signal detected by the block. An enable signal of the second counter is controlled with a signal indicative of an effective period of images, and addresses of a memory are controlled by the first and second counters.
Japanese Patent No. 2740364 (B2) (Japanese Patent Application Publication No. 4-304787) has suggested an apparatus for inserting a title image, including a memory storing image data, a vertical counter which receives a horizontal synchronization signal of an input video signal as a clock signal, and a vertical synchronization signal of the input video signal as a reset signal, and outputs address data with which image data in a first address range is read out of the memory, a scroll counter which receives the horizontal synchronization signal as a clock signal, resets itself at a cycle different from that of the vertical counter, and outputs address data with which image data in a second address range different from the first address range, a switch for selectively switching the address data transmitted from the vertical and scroll counters, and stores the selected one into the memory, a control circuit which operates in accordance with the vertical synchronization signal of the input video signal, and controls the switch in accordance with scroll commands, and means for inserting a title image signal including the image data read out of the memory, into the input video signal.